Research team creates 7 nm silicon fabrication process & test chips

This week IBM announced the tiniest transistors ever made

Using technology developed at IBM’s Almaden Research Center in San Jose and New York laboratories in collaboration with GlobalFoundries and Samsung, the company’s scientists created a “test” chip with transistors 7 nanometers in size.

The test chip is built on a platform of silicon, but on top is a layer of silicon germanium, a material pioneered by IBM. A technique called extreme ultraviolet lithography was used to create the patterns for the chip. To create some of the necessary material, IBM used chemicals developed at Almaden lab.

Current semiconductor manufacturing uses 22 (2012) and 14 (2014) nanometer fabrication processes. The next generation of processors are expected to use 10 (2016-2017) nanometer fabrication not yet available. As a comparison point, a strand of DNA is 2.5 nanometers in width and a human hair is 80,000 nanometers wide.

Silicon is the principle material used to create CPUs, Memory, Flash Storage and Solar Cells. All use monocrystalline or polycrystalline silicon with precise uniform chemical characteristics.

The process used to create a monocrystalline or polycrystalline silicon substrate begins by mining Silicon Dioxide (sand). The sand is heated in a furnace at 1500 to 2000C, resulting in Metallurgical Grade Silicon (MG-Si) or 97% pure silicon.

MG-Si silicon is further purified with the goal to bring impurities below the parts-per-billion level.

The MG-Si silicon is ground to a fine powder and reacted with gaseous hydrogen chloride in a fluidized bed reactor at 300°C to give a liquid compound of silicon called trichlorosilane (TCS).

Impurities such as iron (Fe), aluminium (Al), boron (B) and phosphorous also react to give their chlorides, which are then removed by fractional distillation. The purified TCS is vaporised and reacted with hydrogen (H2) gas at 1,100°C to transform into elemental silicon. This polysilicon has contamination levels of less than .001 ppb.

During the reaction, silicon is deposited on the surface of an electrically heated ultra-pure silicon rod to produce a silicon ingot. The end result is referred to as electronic-grade silicon, and has a purity of 99.999999 per cent.


Although pure to a very high degree, raw electronic-grade silicon has a polycrystalline structure. In other words, it’s made up of lots of small silicon crystals, with defects called grain boundaries between them. Because these anomalies affect local electronic behaviour, polycrystalline silicon is unsuitable for semiconductor manufacturing. To turn it into a usable material, the silicon must be turned into single crystals that have a regular atomic structure. A process known as “Crystal Growing” transforms polycrystalline silicon into samples with a singular crystal orientation, known as ingots.

The Polysilicon is mechanically divided into 1 to 3 inch pieces and undergoes stringent surface etching and cleaning in a clean room environment. The pieces are then packed into quartz crucibles for meltdown (at 1420C) in a CZ furnace. A monocrystalline Silicon seed is installed into a seed shaft in the upper chamber of the furnace. Slowly, the seed is lowered so that it dips approximately 2mm into the Silicon melt. Next, the seed is slowly retracted from the surface allowing the melt to solidify at the boundary. As the seed pulls the Silicon from the melt, both the crucible and the seed are rotated in opposite directions to allow for an almost round crystal to form. Once the proper crystal diameter is achieved, the seed lift is increased. This, along with the heat transfer from heater elements will control the diameter of the crystal.

During the growth process, the crucible slowly dissolves Oxygen into the melt that is incorporated into the final crystal in typical concentrations of around 25ppma. Intentional additions of dopants control the resistivity distribution of the final crystal. In addition to pull speed and heat transfer at the solid-liquid interface, heat dissipation during crystal cooling strongly determines microscopic defect characteristics in the final crystal.

Different Crystal Growing Methods

Horizontal gradient freeze method – gradient freeze technique is a static technique where the melt is gradually solidified by the movement of a temperature gradient along the melt. In this technique a sealed tube holds the starting materials, e.g. highly pure Ga and As (both 6-9 9s pure). The Ga is placed in a quartz crucible at one end of the furnace, and the As is located at the other end. Separating the two substances is a porous barrier which will allow As vapor to react with the Ga. The quartz tube is placed in a two zone furnace where the section containing the As is held at about 620C, while the section with Ga is ramped between 1238C and 1270C. The temperature in the second furnace is adjusted slightly to melt only a portion of the seed crystal. When the crystal is formed, it must be cooled slowly and evenly to avoid stress induced dislocations.

Horizontal Bridgeman method – In this method the furnace is moved along the length of the quartz tube such that the solidification of the melt starting from the seed crystal is achieved as the seed moved from the hotter to the colder section of the furnace. The shape of the crystal is constrained by the walls of the tube. The crystals are typically D-shaped and are seeded in the direction. In general, significantly lower thermal stresses can be obtained in horizontal Bridgeman technique than with the CZ technique. Dislocation densities also tend to be less (~600 cm-2).

Vertical Bridgeman method – In vertical Bridgeman growth the quartz or PBN crucible contains the seed in a well at the bottom and polycrystaline material above it. For growth to occur, the initial charge and a portion of the seed is melted and the crucible is lowered slowly into the bottom section of the furnace. Instead of moving the crucible the furnace can be moved relative to the crucible.

Vertical Gradient Freeze – In vertical gradient freeze (VGF) technique, the crucible and the furnace are kept stationary and the growth is achieved y slowly cooling the melt in an appropriate temperature gradient. One of the principal advantages of the VGF technique is the reduced axial and radial temperature gradients which translate into low dislocation densities of ~ 20 cm-2.

Czochralski Pulling Method – One of the most important techniques for the growth of large round single crystals. A seeded crystal is withdrawn from the melt and is rotated to maintain thermal geometry and cylindrical geometry. The seed is dipped into the melt whose temperature is lowered until a small amount of crystalline material is solidified. The seed is then slowly withdrawn from the melt at the rate of 1 to 10 mm per hour. the melt temperature is lowered slowly and the diameter of the crystal increases. Once the desired diameter is reached, the lowering of the temperature is stopped. Growth at a constant diameter is maintained till the desired length is grown. CZ technique has difficulties when the melt is composed of different elements. Decomposition of the melt can occur. The liquid encapsulation technique can be utilized to provide counter pressure to elements within the melt trying to evaporate. The encapsulant must have low vapor pressure, low viscosity, density lower than that of the melt, and should not mix or react with the melt or the crucible, and should melt before significant decomposition of the poly material occurs. B2O3 is commonly used as an encapsulant.

For modern CZ pulling systems, those variables can be accurately predicted by numerical simulations which allow designing the geometrical and thermal configuration of the CZ puller to the desired outcome of the crystals. Once the growth process is complete, the crystal is cooled inside the furnace for up to 7 hours. This gradual cooling allows the crystal lattice to stabilize and makes handling easier before transport to the next operation. For some applications, it is important to have even lower concentrations of impurity atoms (eg. Oxygen) than what can be achieved by CZ crystal growth. In this case, Float Zone Crystal Growth is used. In this process the end of a long polysilicon rod is locally melted and brought in contact with a monocrystalline Silicon seed. The melted zone slowly migrates through the poly rod leaving behind a final uniform crystal.

Ingots coming from crystal growing are slightly over-sized in diameter and typically not round. Hence, a machine employing a grindwheel shapes the ingot to the precision needed for wafer diameter control. Other grinding wheels are then used to carve a characteristic notch or a flat in order to define the proper orientation of the future wafer versus a particular crystallographic axis.

Wafer shaping involves a series of precise mechanical and chemical process steps that are necessary to turn the ingot segment into a functional wafer. It is during these steps that the wafer surfaces and dimensions are perfected to exacting detail. Each step is designed to bring the wafer into compliance with each customer specification. The first of these critical steps is Multi-Wiring Slicing. The dominant state of the art slicing technology is Multi-Wire Sawing (MWS). Here, a thin wire is arranged over cylindrical spools so that hundreds of parallel wire segments simultaneously travel through the ingot. While the saw as a whole slowly moves through the ingot, the individual wire segments conduct a translational motion always bringing fresh wire into contact with the Silicon. The sawing effect is actually achieved by SiC or other grinding agents that run along the rotating wire. After MWS the wafers are cleaned and consolidated into process lots and transported to the next operation. The sideward deflection of the wire saw can lead to marks or “waviness” on the wafer surface and wire-to-wire thickness variations cause wafer thickness variations of up to several microns. Wafers are thus exposed to a complex polishing process.

State of the art front surface polishing is performed generally in a two step process. One mechanical polishing step (lapping) to create flatness followed by a chemical etch to create smoothness. After polishing, the wafers are subjected to a final clean. Lapping the wafers removes saw marks and surface defects from the front and backside of the wafers, thins the wafer to spec and relieves much of the stress accumulated in the wafer during the sawing process. Edge rounding is normally done before or after lapping and is very important to the structural integrity of the wafer. The edges of 200mm and 300mm wafers are rounded even in the notch area. On the best prime wafers the edges themselves are also highly polished, a step that can improve cleaning results on wafers and reduce breakage up to 400%. Process Specialties has seen a notable yield differential between poorly and perfectly edge rounded material.

For many applications, the quality of a polished wafer is not sufficient. This is mainly due to defects generated during crystal growth in the bulk of the wafer. These defects, when they are within a few microns to the surface, can deteriorate the performance of devices built on top. Presently, the best solution to this problem is to deposit an additional layer of high purity Silicon on the top of a polished wafer substrate (an Epi Layer).

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